1. Field of the Invention
The present invention relates to a method of fabricating a field effect transistor (FET) with a fin structure, and, particularly, to a method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (Fin-FET) has been developed to replace planar MOS transistors. The three-dimensional structure of a fin-FET can increase the overlapping area between the gate and the fin structure of the silicon substrate for scaling down the size and also improve the short channel effect with a thinner fin body. In certain integrated circuits, a double-gate transistor and a tri-gate transistor can be both disposed on a common substrate for improving performance and yield. The double-gate transistor has two gates on the two opposite sidewalls of a fin structure, i.e. two independent gate channels, and each gate can be independently controlled for electrical properties. The tri-gate transistor has a single gate including a gate material layer continuously covering the two opposite sidewalls and the top of a fin structure, i.e. a composite gate channel.
With the demand for a common substrate on which both a double-gate and a tri-gate transistors are disposed, there is still a need for a novel method of fabricating a double-gate and a tri-gate transistors to be more convenient and economical.